I Finally Understand Why One Wafer Can Become Thousands of Chips

I have spent a lot of time over the past year learning about semiconductors, talking to people who understand this industry far better than I do, studying manufacturing processes, looking at foundries, asking questions about capacity, and trying to understand what it would actually take to build semiconductor companies rather than simply talk about them, but there was one very basic concept that, for whatever reason, had never completely clicked in my head until recently.

I kept hearing people talk about semiconductor factories in terms of wafers, with numbers such as 10,000 wafers a month, 20,000 wafers a month, or 40,000 wafers a month, and somewhere in the back of my mind I was still treating a wafer almost like it represented a single chip, as though a factory capable of processing 20,000 wafers was essentially producing something close to 20,000 chips.

Once I finally understood what a wafer actually represents, that entire mental model fell apart, because a semiconductor wafer is not one chip at all; it is a manufacturing surface on which many copies of a circuit are fabricated at the same time, and depending on how large those individual circuits are, a single wafer can eventually become dozens, hundreds, or even thousands of individual semiconductor dies.

Intel describes a wafer as the thin circular piece of semiconductor material on which integrated circuits are fabricated, while a die is an individual integrated circuit that is later separated from that wafer, which means the relationship is not one wafer to one chip, but one wafer to many potential dies.

That sounds incredibly basic once somebody explains it, but understanding it changed how I think about semiconductor manufacturing, because suddenly numbers such as wafer capacity, die size, yield, packaging, and cost per usable chip started connecting to one another as parts of the same system.

20,000 Wafers Does Not Mean 20,000 Chips

Imagine somebody tells you that a semiconductor fab can process 20,000 wafers every month, because if you are unfamiliar with the manufacturing side of the industry, 20,000 sounds like the production number you need to understand, when in reality it is only the beginning of the calculation.

The first question should be what size wafer the factory is processing, the next question should be how large each individual die is, and after that you need to know how many complete dies can physically fit on the wafer, what percentage of those dies survive fabrication and testing, how many dies are required for each finished product, and what happens during assembly and final test before anything is ready to ship to a customer.

This is important because the semiconductor industry itself frequently talks about capacity in wafers rather than finished chips, and some of the numbers are enormous; for example, TSMC says the manufacturing facilities it managed with its subsidiaries exceeded 17 million 12-inch-equivalent wafers of annual capacity in 2025, but that figure is a measurement of manufacturing capacity rather than the number of finished semiconductor devices coming out of those factories.

Depending on the products being manufactured, those millions of wafers can eventually represent many times that number of individual dies, which is why simply comparing two fabs by the number of wafers they process can be misleading if they are producing completely different types of semiconductors.

A factory making relatively small power-management or communications devices might get a very large number of dies from each wafer, while a factory manufacturing an enormous high-performance processor might get dramatically fewer, even if both products begin on a wafer with exactly the same diameter.

That was the first thing that finally clicked for me: a wafer is better understood as manufacturing real estate, and the die is the amount of that real estate consumed by one copy of the design.

A Wafer Is Manufacturing Real Estate

A modern 300 mm wafer is approximately 12 inches in diameter, which gives semiconductor manufacturers a large circular surface on which the same circuit can be repeated many times before the wafer is eventually cut apart into individual dies. Intel identifies 300 mm as the diameter used for modern high-volume silicon wafer manufacturing.

The easiest analogy I can think of is a sheet of material from which you are cutting identical parts, because if every part is tiny, you can fit a lot of them onto that sheet, while if every part is enormous, you can fit far fewer, even though the size of the original sheet never changed.

The difference with semiconductor manufacturing is that the geometry becomes considerably more complicated because the wafer is circular, the dies are generally rectangular, complete dies cannot simply hang over the edge of the wafer, manufacturing needs space between dies for separation, and additional process and test structures can consume some of the available area.

Still, the basic relationship is straightforward enough that you can understand the economics without becoming a semiconductor engineer: smaller die means more potential dies per wafer, while larger die means fewer potential dies per wafer.

To see how dramatic that difference can become, consider a simplified 300 mm wafer and ignore some of the process-specific details for a moment; using a common geometric approximation for gross dies per wafer, a hypothetical 25-square-millimeter die could produce roughly 2,700 gross dies, a 100-square-millimeter die could produce roughly 640, while a much larger 600-square-millimeter die might produce only around 90.

Those numbers are illustrations rather than production forecasts, because the actual number depends on the exact die dimensions, wafer edge exclusion, spacing between dies, test structures, and the specific manufacturing process, but the example shows why asking only for wafer capacity leaves out one of the most important pieces of information.

If a factory processes 20,000 wafers every month, the theoretical output could look completely different depending on whether the product consumes 25 square millimeters of silicon or 600 square millimeters, which means the same 20,000-wafer production number can describe radically different amounts of potential product.

Die Size Changes Everything

Once I understood dies per wafer, I started understanding why semiconductor designers care so much about die area, because reducing the size of a die is not only about making a physically smaller chip; it can change the number of products you can manufacture from the same amount of wafer capacity and therefore change the economics of the entire business.

There is another complication, however, because fitting a die onto a wafer does not mean that die actually works.

Semiconductor fabrication involves an extraordinary sequence of manufacturing steps, and defects can occur during that process, which is why the industry pays so much attention to something called yield.

Intel defines yield as the percentage of usable dies produced from a processed wafer, and notes that yield varies based on factors including die size and defect density, which is the number of defects occurring within a particular area of silicon.

This is where the math becomes much more interesting, because what really matters economically is not the number of dies physically printed onto the wafer, but the number of good dies that survive manufacturing and testing.

Imagine that our hypothetical 100-square-millimeter design gives us approximately 640 gross dies on a 300 mm wafer, and imagine purely for illustration that the manufacturing process delivers a 90 percent usable-die yield; instead of having 640 good dies, we would have roughly 576.

Now imagine a much larger 600-square-millimeter design where we begin with only about 91 gross dies and, again purely as an illustration rather than a prediction for any specific process, the yield is 70 percent; now we have only about 64 usable dies coming from the same size wafer.

That means the important manufacturing equation is not simply:

Wafer → chips

It is closer to:

Wafer → gross dies → good dies → packaged devices → tested products

Once I started thinking about semiconductor production this way, the entire industry became easier to understand because every stage reduces or transforms what came before it, and the ultimate business question is not how many patterns you managed to print onto silicon, but how many products you can reliably deliver to customers at an economically sustainable cost.

Yield Is Where the Beautiful Spreadsheet Meets Reality

This is also where semiconductor manufacturing becomes much less forgiving than a simple spreadsheet, because somebody can calculate a theoretically impressive number of dies per wafer, multiply that by the number of wafers they expect to process, and arrive at an enormous production number that looks fantastic until actual manufacturing yield enters the equation.

If your process has more defects than expected, your good-die count falls; if the die grows because the design needs additional circuitry, fewer dies fit on each wafer; if packaging is more difficult than anticipated, additional units disappear later in the process; and if the final product contains multiple dies, the relationship between one good die and one finished product becomes even more complicated.

That last point is becoming particularly important because a modern semiconductor package does not necessarily contain only one die, and Intel describes the second half of semiconductor manufacturing as assembly and test, where one or more silicon dies can be mounted into a package before undergoing additional testing and validation.

Advanced semiconductor architectures are taking this much further by combining multiple chiplets and components into a single package, which means that a finished processor can increasingly be thought of as a small system assembled from several pieces of silicon rather than one enormous monolithic die. Intel Foundry describes advanced packaging as a way to integrate multiple chiplets and components into a single high-density package, with testing required to identify known-good dies before those components reach final assembly.

This creates a very different manufacturing problem, because now you are not simply asking whether one die works; you may need several known-good dies, potentially manufactured on different process technologies, assembled together with memory, substrates, interconnects, power delivery, thermal management, and packaging that all have to work as one product.

For AI and other high-performance systems, that shift is becoming increasingly important, and Intel described the industry in July 2026 as moving beyond reliance on a single massive chip toward systems made from multiple interconnected chiplets.

Why Wafer Capacity Can Be Misleading

This is why I now hear semiconductor capacity numbers differently, because when somebody tells me a fab is expanding from 20,000 wafers per month to 40,000 wafers per month, I understand that they have told me something important about manufacturing capacity, but they have not yet told me how many finished devices that factory can produce.

I still need to know what kind of wafer we are talking about, what process is being used, what products are being manufactured, how large the dies are, what the manufacturing yield looks like, and whether each finished product requires one die or several.

The distinction matters even more today because semiconductor manufacturing capacity is expanding rapidly as AI, high-bandwidth memory, data centers, regional supply-chain strategies, and new manufacturing investments increase demand for fab capacity around the world.

SEMI's current 300 mm Fab Outlook projects total installed 300 mm manufacturing capacity to grow approximately 7 percent in 2026 and continue growing at roughly that pace through 2029, while its June 2026 outlook for 300 mm memory manufacturing projects 4.1 million wafers per month of memory capacity in 2026 and 4.2 million in 2027, driven heavily by demand for HBM, DDR5, AI accelerators, and data infrastructure.

An earlier SEMI forecast also projected advanced-process capacity at 7 nm and below to rise from approximately 850,000 wafers per month in 2024 to 1.4 million wafers per month by 2028, with AI identified as one of the central drivers behind that expansion.

Those are enormous industrial numbers, but the lesson I am taking from them is that wafer capacity is the beginning of the semiconductor production story rather than the end of it.

The Economics Are Hidden Inside the Wafer

The next thing that started making sense to me was why yield and die size have such an enormous influence on semiconductor economics, because once the wafer has been processed, the cost of that wafer has to be spread across the usable dies that come out of it.

At the simplest conceptual level, you can think about it like this:

Approximate silicon cost per good die = wafer processing cost ÷ good dies per wafer

That is intentionally simplified because an actual semiconductor company's economics also include design costs, masks, intellectual property, packaging, testing, substrates, memory, engineering, qualification, logistics, equipment depreciation, and many other expenses, but the simplified equation explains why the relationship between die size and yield is so important.

If two designs are manufactured on comparable wafers at comparable processing costs, but one produces 500 usable dies and another produces only 100, the cost of the wafer is being spread across a dramatically different number of products.

This is one reason chiplets have become such an interesting architectural option for some high-performance products, because instead of building every function onto one extremely large monolithic die, designers can sometimes divide the system into smaller dies and connect them through advanced packaging, potentially improving manufacturing flexibility and allowing different functions to use the process technology that makes the most economic sense.

Intel Foundry explicitly describes this type of architecture as a way to break large monolithic chips into smaller chiplets to improve yield and cost while also allowing functions that do not benefit as much from the newest manufacturing geometry to remain on older process technologies.

The system does not become magically cheaper simply because somebody uses chiplets, because packaging, interconnects, testing, thermal management, and assembly all introduce their own costs and complexity, but it demonstrates how wafer economics can influence architecture itself.

The geometry of the die eventually becomes a business decision.

The 20,000-Wafer Example Looks Completely Different Now

Going back to the number that originally caused this entire thing to click for me, imagine again that a semiconductor manufacturer has access to 20,000 300 mm wafers every month, and then apply our simplified examples to see why that number alone tells us so little.

With a hypothetical 25-square-millimeter die producing approximately 2,694 gross dies per wafer, and an illustrative 90 percent usable-die yield, you would end up with roughly 2,425 good dies per wafer, which across 20,000 wafers would represent approximately 48.5 million good dies.

With a hypothetical 100-square-millimeter design producing about 640 gross dies and the same illustrative 90 percent yield, those same 20,000 wafers would represent approximately 11.5 million good dies.

With the hypothetical 600-square-millimeter design producing roughly 91 gross dies and our illustrative 70 percent yield, those same 20,000 wafers would represent only about 1.27 million good dies.

The assumptions in those examples are deliberately simplified and should not be treated as estimates for any specific semiconductor product, but the magnitude of the difference is the point: the same factory, the same wafer diameter, and the same 20,000 wafers can translate into tens of millions of usable dies for one design and barely more than a million for another.

That is an extraordinary difference in production output hidden behind exactly the same headline capacity number.

This Changed the Questions I Ask

The biggest thing I have taken away from learning this is not that I now know how to calculate dies per wafer, because semiconductor manufacturing is far more complicated than any simple formula can capture; what changed is that I now know which questions need to come next when somebody presents a manufacturing number.

When I hear that a company has secured wafer capacity, I want to know the wafer diameter and the process technology, because 200 mm and 300 mm manufacturing serve different markets and architectures; I want to know the approximate die area and gross dies per wafer, because those numbers tell me how much manufacturing real estate each product consumes; I want to understand the expected yield and how mature the manufacturing process is, because theoretical dies and known-good dies are not the same thing; and I want to understand packaging, testing, and whether the finished product contains one die or several, because fabrication is only one part of actually delivering a semiconductor device.

I also want to know what somebody means when they say they have 20,000 wafers of “capacity,” because installed factory capacity, available manufacturing allocation, wafer starts, processed wafers, and finished good products are all different measurements, and treating them as interchangeable can make a semiconductor company's scale look either much larger or much smaller than it really is.

For a founder, investor, customer, or anyone trying to understand this industry, those distinctions matter because a semiconductor company is not simply designing an object called a chip; it is participating in a production system that begins with design and process technology, moves through wafer fabrication and yield, continues through assembly, packaging, testing, qualification, and supply chain, and finally ends with a product that somebody can actually use.

That system is where the economics live.

The Part I Was Missing

I originally thought learning about semiconductors meant learning about transistors, architectures, process nodes, RF, memory, processors, materials, and all of the other technologies that make a chip work, but the deeper I get into this industry, the more I realize that understanding how something gets manufactured can be just as important as understanding what it does.

A brilliant semiconductor architecture that cannot achieve acceptable yield is a problem, a chip that is technically impressive but consumes too much wafer area can become an economic problem, a design that works perfectly before packaging can still run into assembly or thermal problems, and a company that has a compelling product but cannot secure enough manufacturing capacity can still fail to deliver it.

That is why understanding wafers changed the way I think about semiconductor scale, because the wafer sits at the intersection between design and physical production, and once you understand that a wafer is a finite piece of manufacturing real estate rather than one giant chip, many other parts of the industry begin making more sense.

Now, when somebody tells me that a factory can produce 20,000 or 40,000 wafers every month, I no longer automatically try to translate that number into chips, because I know there is an entire chain of questions sitting underneath it.

I want to know what we are building, how large the die is, how many copies fit on the wafer, how many survive, how many dies go into each package, and how many finished products actually come out the other side.

Only then do I really know what 20,000 wafers means.

Frequently Asked Questions

How many chips can be made from one semiconductor wafer?

There is no single number because the answer depends on wafer diameter, die dimensions, manufacturing layout, process technology, and yield, which means one wafer might eventually produce dozens of very large dies, hundreds of medium-sized dies, or thousands of relatively small dies. Intel's explanation of semiconductor terminology similarly distinguishes the wafer from the individual dies fabricated across its surface and notes that yield depends partly on die size and defect density.

What is the difference between a wafer, a die, and a chip?

A wafer is the circular semiconductor substrate used during fabrication, while a die is one individual integrated circuit created on that wafer and separated after fabrication; the term chip is used somewhat loosely in everyday conversation and can refer to the die itself, although a commercially shipped chip commonly includes the die or dies assembled into a package that provides electrical and physical connections.

What is a 300 mm wafer?

A 300 mm wafer is approximately 12 inches in diameter and is widely used for modern high-volume semiconductor production, providing considerably more manufacturing area than older, smaller wafer formats and therefore allowing many dies to be fabricated simultaneously.

What does semiconductor yield mean?

Semiconductor yield refers to the percentage of manufactured dies that are usable, which means a wafer containing hundreds of physically complete dies will not necessarily produce the same number of sellable devices because some dies can fail fabrication or electrical requirements; Intel notes that yield varies according to factors including die size and defect density.

Does 20,000 wafers per month mean 20,000 chips per month?

No, because each wafer can contain many individual dies, and the eventual number of usable products depends on die size, gross dies per wafer, yield, packaging configuration, and testing, so a factory processing 20,000 wafers could potentially manufacture millions of individual dies rather than only 20,000 chips.

Why do large dies generally cost more?

Large dies consume more wafer area, which means fewer complete copies fit onto each wafer, while their larger area can also expose each die to a greater probability of encountering a manufacturing defect; because the wafer processing cost must ultimately be distributed across the usable dies produced, fewer good dies can increase the silicon cost associated with each usable device. Intel identifies both die size and defect density as factors affecting semiconductor yield.

Can one finished chip contain several dies?

Yes, and this is increasingly important in high-performance computing and AI systems, because advanced packaging technologies can combine multiple chiplets, memory components, and other dies within one package, allowing what the customer sees as one processor or semiconductor product to contain an entire interconnected system of chips.

Why are chiplets becoming important?

Chiplets can allow designers to divide a large semiconductor system into smaller functional dies, potentially improving manufacturing yield, allowing different functions to use different process technologies, and giving system architects more flexibility than a single large monolithic die, although these benefits come with additional packaging, interconnect, testing, thermal, and assembly challenges.

Sources

Intel, Explaining Common Chip Terms

Intel, How Silicon Die Become Chip Packages

Intel Foundry, Advanced Packaging Innovations

Intel Foundry, Packaging & Test Research

Intel Foundry, Cutting-edge Process Technologies for Data Center

TSMC, Fab Capacity and 2025 Annual Report

SEMI, 300mm Fab Outlook

SEMI, 2026 300mm Memory Capacity Outlook

Themex Studio, Braun Documentation